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Si5040
Revision 0.86 to Revision 1.2
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Removed sections 5.8.3 and 6.4.3 since fast
acquisition is no longer supported.
Clarified operation of Register 7[3:2] in register
descriptions and "5.8.1. SQM LOL" on page 24.
Updated part number in "15. Ordering Guide" on
page 103.
Added information on voltage application to VDD
and VDDIO in pin descriptions.
Removed reference to Mode 7 from Register 134
since Mode 7 does not exist.
Changed all SCL references to SCK and all SDA
reference to SD for consistency.
Revision 1.2 to Revision 1.3
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Clarified RX LOL feature in sections “5.8.1.1.
Dynamic Register Control” and “5.8.2. Frequency
LOL”
Added section “5.8.3. Acquisition Time
Enhancement”
Clarified TX LOL feature in sections “6.4.1.1.
Dynamic Register Control” and “6.4.2. Frequency
LOL”
Added section “6.4.3. Acquisition Time
Enhancement”
Changed TX and RX path data rate minimum
parameters from 9.9 to 9.8 Gbps to allow for 9.8304
Gbps CPRI data rate
Rev. 1.3
107
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